1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches used in forming a set of dummy mask pillars in a semiconductor device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin-type field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
In current art approaches, middle of line (MOL) processing for 14 nm (or smaller) FinFET fully encapsulates the gate in nitride. A contact to SD is etched through oxide, selectively to nitride (TS level). This contact may be self-aligned. After TS metallization and CMP, an Inter-Layer Dielectric (ILD) film is deposited, and the S/D contact to TS and gate contact are processed. However, this becomes increasingly problematic at sub 10 nm processing due to density requirements.